Home
last modified time | relevance | path

Searched refs:SCG_FIRCCSR_FIRCERR_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c566 if (SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) in CLOCK_InitFirc()
599 SCG->FIRCCSR = SCG_FIRCCSR_FIRCERR_MASK; in CLOCK_DeinitFirc()
Dfsl_clock.h1388 return (bool)(SCG->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK); in CLOCK_IsFircErr()
1396 SCG->FIRCCSR |= SCG_FIRCCSR_FIRCERR_MASK; in CLOCK_ClearFircErr()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h16948 #define SCG_FIRCCSR_FIRCERR_MASK (0x4000000U) macro
16954 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK)
DRV32M1_zero_riscy.h17776 #define SCG_FIRCCSR_FIRCERR_MASK (0x4000000U) macro
17782 … (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK)