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Searched refs:SCG_CSR_DIVSLOW_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h16253 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
16273 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)
DRV32M1_zero_riscy.h17081 #define SCG_CSR_DIVSLOW_MASK (0xFU) macro
17101 … (((uint32_t)(((uint32_t)(x)) << SCG_CSR_DIVSLOW_SHIFT)) & SCG_CSR_DIVSLOW_MASK)