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Searched refs:RSIM_WOR_DURATION_WOR_DSM_DURATION_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h15188 #define RSIM_WOR_DURATION_WOR_DSM_DURATION_MASK (0xFFFFFFU) macro
15190 …t32_t)(x)) << RSIM_WOR_DURATION_WOR_DSM_DURATION_SHIFT)) & RSIM_WOR_DURATION_WOR_DSM_DURATION_MASK)
DRV32M1_zero_riscy.h16016 #define RSIM_WOR_DURATION_WOR_DSM_DURATION_MASK (0xFFFFFFU) macro
16018 …t32_t)(x)) << RSIM_WOR_DURATION_WOR_DSM_DURATION_SHIFT)) & RSIM_WOR_DURATION_WOR_DSM_DURATION_MASK)