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Searched refs:RSIM_DSM_TIMER_DSM_TIMER_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h15086 #define RSIM_DSM_TIMER_DSM_TIMER_MASK (0xFFFFFFU) macro
15088 … (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_TIMER_DSM_TIMER_SHIFT)) & RSIM_DSM_TIMER_DSM_TIMER_MASK)
DRV32M1_zero_riscy.h15914 #define RSIM_DSM_TIMER_DSM_TIMER_MASK (0xFFFFFFU) macro
15916 … (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_TIMER_DSM_TIMER_SHIFT)) & RSIM_DSM_TIMER_DSM_TIMER_MASK)