Home
last modified time | relevance | path

Searched refs:RSIM_DSM_CONTROL_DSM_WOR_FINISHED_SHIFT (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h15100 #define RSIM_DSM_CONTROL_DSM_WOR_FINISHED_SHIFT (2U) macro
15101 …_DSM_WOR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_WOR_FINISHED_SHIFT))…
DRV32M1_zero_riscy.h15928 #define RSIM_DSM_CONTROL_DSM_WOR_FINISHED_SHIFT (2U) macro
15929 …_DSM_WOR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_WOR_FINISHED_SHIFT))…