Home
last modified time | relevance | path

Searched refs:RSIM_DSM_CONTROL_DSM_WOR_FINISHED_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h15099 #define RSIM_DSM_CONTROL_DSM_WOR_FINISHED_MASK (0x4U) macro
15101 …int32_t)(x)) << RSIM_DSM_CONTROL_DSM_WOR_FINISHED_SHIFT)) & RSIM_DSM_CONTROL_DSM_WOR_FINISHED_MASK)
DRV32M1_zero_riscy.h15927 #define RSIM_DSM_CONTROL_DSM_WOR_FINISHED_MASK (0x4U) macro
15929 …int32_t)(x)) << RSIM_DSM_CONTROL_DSM_WOR_FINISHED_SHIFT)) & RSIM_DSM_CONTROL_DSM_WOR_FINISHED_MASK)