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Searched refs:RSIM_DSM_CONTROL_DSM_TIMER_CLR_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h15162 #define RSIM_DSM_CONTROL_DSM_TIMER_CLR_MASK (0x8000000U) macro
15164 …t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_TIMER_CLR_SHIFT)) & RSIM_DSM_CONTROL_DSM_TIMER_CLR_MASK)
DRV32M1_zero_riscy.h15990 #define RSIM_DSM_CONTROL_DSM_TIMER_CLR_MASK (0x8000000U) macro
15992 …t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_TIMER_CLR_SHIFT)) & RSIM_DSM_CONTROL_DSM_TIMER_CLR_MASK)