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Searched refs:RSIM_CONTROL_RSIM_CGC_ZIG_EN_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/middleware/wireless/framework/XCVR/RV32M1/cfgs_rv32m1/
Dfsl_xcvr_zgbe_config.c30 .scgc5_clock_ena_bits = RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK | RSIM_CONTROL_RSIM_CGC_ZIG_EN_MASK,
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h14921 #define RSIM_CONTROL_RSIM_CGC_ZIG_EN_MASK (0x20000000U) macro
14927 …t32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_CGC_ZIG_EN_SHIFT)) & RSIM_CONTROL_RSIM_CGC_ZIG_EN_MASK)
DRV32M1_zero_riscy.h15749 #define RSIM_CONTROL_RSIM_CGC_ZIG_EN_MASK (0x20000000U) macro
15755 …t32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_CGC_ZIG_EN_SHIFT)) & RSIM_CONTROL_RSIM_CGC_ZIG_EN_MASK)