Home
last modified time | relevance | path

Searched refs:RSIM_CONTROL_RSIM_CGC_GEN_EN_MASK (Results 1 – 9 of 9) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/middleware/wireless/framework/XCVR/RV32M1/cfgs_rv32m1/
Dfsl_xcvr_gfsk_bt_0p5_h_1p0_config.c31 ….scgc5_clock_ena_bits = RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK | RSIM_CONTROL_RSIM_CGC_GEN_EN_MASK, /*…
Dfsl_xcvr_gfsk_bt_0p5_h_0p7_config.c31 ….scgc5_clock_ena_bits = RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK | RSIM_CONTROL_RSIM_CGC_GEN_EN_MASK, /*…
Dfsl_xcvr_gfsk_bt_0p7_h_0p5_config.c32 ….scgc5_clock_ena_bits = RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK | RSIM_CONTROL_RSIM_CGC_GEN_EN_MASK, /*…
Dfsl_xcvr_msk_config.c32 ….scgc5_clock_ena_bits = RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK | RSIM_CONTROL_RSIM_CGC_GEN_EN_MASK, /*…
Dfsl_xcvr_gfsk_bt_0p5_h_0p5_config.c32 ….scgc5_clock_ena_bits = RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK | RSIM_CONTROL_RSIM_CGC_GEN_EN_MASK, /*…
Dfsl_xcvr_gfsk_bt_0p3_h_0p5_config.c32 ….scgc5_clock_ena_bits = RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK | RSIM_CONTROL_RSIM_CGC_GEN_EN_MASK, /*…
Dfsl_xcvr_gfsk_bt_0p5_h_0p32_config.c32 ….scgc5_clock_ena_bits = RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK | RSIM_CONTROL_RSIM_CGC_GEN_EN_MASK, /*…
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h14928 #define RSIM_CONTROL_RSIM_CGC_GEN_EN_MASK (0x80000000U) macro
14934 …t32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_CGC_GEN_EN_SHIFT)) & RSIM_CONTROL_RSIM_CGC_GEN_EN_MASK)
DRV32M1_zero_riscy.h15756 #define RSIM_CONTROL_RSIM_CGC_GEN_EN_MASK (0x80000000U) macro
15762 …t32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_CGC_GEN_EN_SHIFT)) & RSIM_CONTROL_RSIM_CGC_GEN_EN_MASK)