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Searched refs:RSIM_CONTROL_RF_OSC_EN_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/middleware/wireless/framework/XCVR/RV32M1/
Dfsl_xcvr.c364 RSIM->CONTROL |= RSIM_CONTROL_RF_OSC_EN_MASK; in rf_osc_startup()
376 RSIM->CONTROL &= ~RSIM_CONTROL_RF_OSC_EN_MASK; in rf_osc_shutdown()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h14864 #define RSIM_CONTROL_RF_OSC_EN_MASK (0x100U) macro
14866 … (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_EN_SHIFT)) & RSIM_CONTROL_RF_OSC_EN_MASK)
DRV32M1_zero_riscy.h15692 #define RSIM_CONTROL_RF_OSC_EN_MASK (0x100U) macro
15694 … (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_EN_SHIFT)) & RSIM_CONTROL_RF_OSC_EN_MASK)