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Searched refs:RR (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_mu.c77 return base->RR[regIndex]; in MU_ReceiveMsg()
Dfsl_mu.h212 return base->RR[regIndex]; in MU_ReceiveMsgNonBlocking()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h14044 …__I uint32_t RR[4]; /**< Receive Register, array offset: 0x40, array … member
DRV32M1_zero_riscy.h14726 …__I uint32_t RR[4]; /**< Receive Register, array offset: 0x40, array … member