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Searched refs:ROSCCSR (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.h1424 return (bool)(SCG->ROSCCSR & SCG_ROSCCSR_ROSCERR_MASK); in CLOCK_IsRtcOscErr()
1432 SCG->ROSCCSR |= SCG_ROSCCSR_ROSCERR_MASK; in CLOCK_ClearRtcOscErr()
1445 uint32_t reg = SCG->ROSCCSR; in CLOCK_SetRtcOscMonitorMode()
1451 SCG->ROSCCSR = reg; in CLOCK_SetRtcOscMonitorMode()
1461 return (bool)(SCG->ROSCCSR & SCG_ROSCCSR_ROSCVLD_MASK); in CLOCK_IsRtcOscValid()
Dfsl_clock.c655 if (SCG->ROSCCSR & SCG_ROSCCSR_ROSCVLD_MASK) /* RTC OSC clock is valid. */ in CLOCK_GetRtcOscFreq()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h16201 …__IO uint32_t ROSCCSR; /**< RTC OSC Control Status Register, offset: 0x4… member
DRV32M1_zero_riscy.h17029 …__IO uint32_t ROSCCSR; /**< RTC OSC Control Status Register, offset: 0x4… member