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Searched refs:QDCTRL (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_tpm.c166 base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK; in TPM_SetupPwm()
433 base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK; in TPM_SetupInputCapture()
481 base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK; in TPM_SetupOutputCompare()
528 base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK; in TPM_SetupDualEdgeCapture()
662 reg = base->QDCTRL; in TPM_SetupQuadDecode()
665 base->QDCTRL = reg; in TPM_SetupQuadDecode()
668 base->QDCTRL |= TPM_QDCTRL_QUADEN_MASK; in TPM_SetupQuadDecode()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h19277 …__IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offse… member
DRV32M1_zero_riscy.h20105 …__IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offse… member