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Searched refs:PHY_FSK_CFG (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/middleware/wireless/framework/XCVR/RV32M1/
Dfsl_xcvr.c692 …XCVR_PHY->PHY_FSK_CFG = mode_config->phy_fsk_cfg | mode_datarate_config->phy_fsk_cfg_mode_datarate… in XCVR_Configure()
695 …XCVR_PHY->PHY_FSK_CFG = mode_config->phy_fsk_cfg | mode_datarate_config->phy_fsk_cfg_mode_datarate… in XCVR_Configure()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h26409 __IO uint32_t PHY_FSK_CFG; /**< PHY Configuration, offset: 0x8 */ member
DRV32M1_zero_riscy.h25565 __IO uint32_t PHY_FSK_CFG; /**< PHY Configuration, offset: 0x8 */ member