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Searched refs:PDDR (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_gpio.c70 base->PDDR &= ~(1U << pin); in GPIO_PinInit()
75 base->PDDR |= (1U << pin); in GPIO_PinInit()
161 base->PDDR &= ~(1U << pin); in FGPIO_PinInit()
166 base->PDDR |= (1U << pin); in FGPIO_PinInit()
/hal_openisa-latest/vega_sdk_riscv/middleware/wireless/framework/XCVR/RV32M1/
Dfsl_xcvr.c2220 GPIOC->PDDR |= 0x18; in XCVR_CoexistenceInit()
2224 GPIOC->PDDR |= 0x0A; in XCVR_CoexistenceInit()
2252 GPIOC->PDDR |= 0x12; in XCVR_CoexistenceInit()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_zero_riscy.h5404 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
7421 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
DRV32M1_ri5cy.h7277 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member