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Searched refs:PCC1_BASE (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.h369 kCLOCK_Edma1 = MAKE_PCC_REGADDR(PCC1_BASE, 0x20),
370 kCLOCK_Rgpio1 = MAKE_PCC_REGADDR(PCC1_BASE, 0x3C),
371 kCLOCK_Xrdc0PacB = MAKE_PCC_REGADDR(PCC1_BASE, 0x58),
372 kCLOCK_Xrdc0MrcB = MAKE_PCC_REGADDR(PCC1_BASE, 0x5C),
373 kCLOCK_Sema421 = MAKE_PCC_REGADDR(PCC1_BASE, 0x6C),
374 kCLOCK_Dmamux1 = MAKE_PCC_REGADDR(PCC1_BASE, 0x84),
376 kCLOCK_Intmux1 = MAKE_PCC_REGADDR(PCC1_BASE, 0x88),
378 kCLOCK_Intmux0 = MAKE_PCC_REGADDR(PCC1_BASE, 0x88),
380 kCLOCK_MuB = MAKE_PCC_REGADDR(PCC1_BASE, 0x90),
381 kCLOCK_Cau3 = MAKE_PCC_REGADDR(PCC1_BASE, 0xA0),
[all …]
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h14437 #define PCC1_BASE (0x41027000u) macro
14439 #define PCC1 ((PCC_Type *)PCC1_BASE)
14441 #define PCC_BASE_ADDRS { PCC0_BASE, PCC1_BASE }
DRV32M1_zero_riscy.h15119 #define PCC1_BASE (0x41027000u) macro
15121 #define PCC1 ((PCC_Type *)PCC1_BASE)
15123 #define PCC_BASE_ADDRS { PCC0_BASE, PCC1_BASE }