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Searched refs:PCC0_BASE (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.h325 kCLOCK_Mscm = MAKE_PCC_REGADDR(PCC0_BASE, 0x4),
326 kCLOCK_Syspm = MAKE_PCC_REGADDR(PCC0_BASE, 0xC),
327 kCLOCK_Max0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x10),
328 kCLOCK_Edma0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x20),
329 kCLOCK_Flexbus = MAKE_PCC_REGADDR(PCC0_BASE, 0x30),
330 kCLOCK_Xrdc0Mgr = MAKE_PCC_REGADDR(PCC0_BASE, 0x50),
331 kCLOCK_Xrdc0Pac = MAKE_PCC_REGADDR(PCC0_BASE, 0x58),
332 kCLOCK_Xrdc0Mrc = MAKE_PCC_REGADDR(PCC0_BASE, 0x5C),
333 kCLOCK_Sema420 = MAKE_PCC_REGADDR(PCC0_BASE, 0x6C),
334 kCLOCK_Dmamux0 = MAKE_PCC_REGADDR(PCC0_BASE, 0x84),
[all …]
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h14433 #define PCC0_BASE (0x4002B000u) macro
14435 #define PCC0 ((PCC_Type *)PCC0_BASE)
14441 #define PCC_BASE_ADDRS { PCC0_BASE, PCC1_BASE }
DRV32M1_zero_riscy.h15115 #define PCC0_BASE (0x4002B000u) macro
15117 #define PCC0 ((PCC_Type *)PCC0_BASE)
15123 #define PCC_BASE_ADDRS { PCC0_BASE, PCC1_BASE }