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Searched refs:PACKET_RAM_CTRL (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/middleware/wireless/framework/XCVR/RV32M1/
Ddbg_ram_capture.c46 …XCVR_MISC->PACKET_RAM_CTRL |= XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK /* Make PKT RAM availa… in dbg_ram_init()
60 XCVR_MISC->PACKET_RAM_CTRL &= ~XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK; /* force to idle */ in dbg_ram_release()
61 …XCVR_MISC->PACKET_RAM_CTRL &= ~(XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK /* Make PKT RAM avai… in dbg_ram_release()
116 temp = XCVR_MISC->PACKET_RAM_CTRL; in unpack_sequential_data()
119 XCVR_MISC->PACKET_RAM_CTRL = temp; in unpack_sequential_data()
164 …xcvr_ctrl_pkt_ram_0_sel = XCVR_MISC->PACKET_RAM_CTRL & ~XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_PAGE_MA… in unpack_simul_data()
165 …xcvr_ctrl_pkt_ram_1_sel = XCVR_MISC->PACKET_RAM_CTRL | XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_PAGE_MAS… in unpack_simul_data()
170 XCVR_MISC->PACKET_RAM_CTRL = xcvr_ctrl_pkt_ram_0_sel; in unpack_simul_data()
175 XCVR_MISC->PACKET_RAM_CTRL = xcvr_ctrl_pkt_ram_1_sel; in unpack_simul_data()
179 …XCVR_MISC->PACKET_RAM_CTRL = xcvr_ctrl_pkt_ram_0_sel; /* leave selection set to bank 0 of packet R… in unpack_simul_data()
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/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h25681 __IO uint32_t PACKET_RAM_CTRL; /**< PACKET RAM CONTROL, offset: 0x1C */ member
DRV32M1_zero_riscy.h24837 __IO uint32_t PACKET_RAM_CTRL; /**< PACKET RAM CONTROL, offset: 0x1C */ member