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Searched refs:MU_SR_RFn_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_mu.h321 …return (base->SR & (MU_SR_TEn_MASK | MU_SR_RFn_MASK | MU_SR_GIPn_MASK | MU_SR_EP_MASK | MU_SR_FUP_… in MU_GetStatusFlags()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h14180 #define MU_SR_RFn_MASK (0xF000000U) macro
14186 …(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)
DRV32M1_zero_riscy.h14862 #define MU_SR_RFn_MASK (0xF000000U) macro
14868 …(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)