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Searched refs:MU_SR_RAIP_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_mu.c160 sr = (MU_SR_RAIP_MASK | MU_SR_RDIP_MASK); in MU_HardwareResetOtherCore()
173 while (!(base->SR & MU_SR_RAIP_MASK)) in MU_HardwareResetOtherCore()
202 sr = (MU_SR_RAIP_MASK | MU_SR_RDIP_MASK); in MU_HardwareResetOtherCore()
215 while (!(base->SR & MU_SR_RAIP_MASK)) in MU_HardwareResetOtherCore()
Dfsl_mu.h52 …kMU_ResetAssertInterruptFlag = MU_SR_RAIP_MASK, /*!< The other core reset assert interrupt pendi…
326 | MU_SR_RDIP_MASK | MU_SR_RAIP_MASK in MU_GetStatusFlags()
369 regMask |= (MU_SR_RDIP_MASK | MU_SR_RAIP_MASK); in MU_ClearStatusFlags()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h14149 #define MU_SR_RAIP_MASK (0x400U) macro
14155 …x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RAIP_SHIFT)) & MU_SR_RAIP_MASK)
DRV32M1_zero_riscy.h14831 #define MU_SR_RAIP_MASK (0x400U) macro
14837 …x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RAIP_SHIFT)) & MU_SR_RAIP_MASK)