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Searched refs:MSCM_CPXCFG0_ICSZ_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h13461 #define MSCM_CPXCFG0_ICSZ_MASK (0xFF000000U) macro
13463 … (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_ICSZ_SHIFT)) & MSCM_CPXCFG0_ICSZ_MASK)
DRV32M1_zero_riscy.h13640 #define MSCM_CPXCFG0_ICSZ_MASK (0xFF000000U) macro
13642 … (((uint32_t)(((uint32_t)(x)) << MSCM_CPXCFG0_ICSZ_SHIFT)) & MSCM_CPXCFG0_ICSZ_MASK)