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Searched refs:MSCM_CFG3_FPU_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h13632 #define MSCM_CFG3_FPU_MASK (0x1U) macro
13638 … (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_FPU_SHIFT)) & MSCM_CFG3_FPU_MASK)
DRV32M1_zero_riscy.h13811 #define MSCM_CFG3_FPU_MASK (0x1U) macro
13817 … (((uint32_t)(((uint32_t)(x)) << MSCM_CFG3_FPU_SHIFT)) & MSCM_CFG3_FPU_MASK)