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Searched refs:MMDVSQ_CSR_USGN_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_mmdvsq.c20 temp &= ~(MMDVSQ_CSR_USGN_MASK | MMDVSQ_CSR_REM_MASK); in MMDVSQ_GetDivideRemainder()
41 temp &= ~(MMDVSQ_CSR_USGN_MASK | MMDVSQ_CSR_REM_MASK); in MMDVSQ_GetDivideQuotient()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_zero_riscy.h13460 #define MMDVSQ_CSR_USGN_MASK (0x2U) macro
13466 … (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_USGN_SHIFT)) & MMDVSQ_CSR_USGN_MASK)