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Searched refs:MMDVSQ_CSR_DZE_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_mmdvsq.h162 base->CSR |= MMDVSQ_CSR_DZE_MASK; in MMDVSQ_SetDivideByZeroConfig()
166 base->CSR &= ~MMDVSQ_CSR_DZE_MASK; in MMDVSQ_SetDivideByZeroConfig()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_zero_riscy.h13474 #define MMDVSQ_CSR_DZE_MASK (0x8U) macro
13480 … (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DZE_SHIFT)) & MMDVSQ_CSR_DZE_MASK)