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Searched refs:MMDVSQ_CSR_DIV_MASK (Results 1 – 1 of 1) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_zero_riscy.h13502 #define MMDVSQ_CSR_DIV_MASK (0x40000000U) macro
13508 … (((uint32_t)(((uint32_t)(x)) << MMDVSQ_CSR_DIV_SHIFT)) & MMDVSQ_CSR_DIV_MASK)