Home
last modified time | relevance | path

Searched refs:MIX_CTRL (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_usdhc.c303 base->MIX_CTRL |= USDHC_MIX_CTRL_AC23EN_MASK; in USDHC_SetTransferConfig()
310 base->MIX_CTRL &= ~USDHC_MIX_CTRL_AC23EN_MASK; in USDHC_SetTransferConfig()
599 mixCtrl = base->MIX_CTRL; in USDHC_SendCommand()
617 base->MIX_CTRL = mixCtrl; in USDHC_SendCommand()
762 base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; in USDHC_Init()
827 if ((base->MIX_CTRL & USDHC_MIX_CTRL_DDR_EN_MASK) != 0U) in USDHC_SetSdClock()
1120 base->MIX_CTRL |= USDHC_MIX_CTRL_DMAEN_MASK; in USDHC_SetAdmaTableConfig()
1190 base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; in USDHC_TransferBlocking()
1200 base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; in USDHC_TransferBlocking()
1284 base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; in USDHC_TransferNonBlocking()
[all …]
Dfsl_usdhc.h1089 base->MIX_CTRL |= USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; in USDHC_EnableAutoTuning()
1093 base->MIX_CTRL &= ~USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; in USDHC_EnableAutoTuning()
1191 base->MIX_CTRL &= ~USDHC_MIX_CTRL_NIBBLE_POS_MASK; in USDHC_EnableDDRMode()
1192 base->MIX_CTRL |= (USDHC_MIX_CTRL_DDR_EN_MASK | USDHC_MIX_CTRL_NIBBLE_POS(nibblePos)); in USDHC_EnableDDRMode()
1196 base->MIX_CTRL &= ~USDHC_MIX_CTRL_DDR_EN_MASK; in USDHC_EnableDDRMode()
1211 base->MIX_CTRL |= USDHC_MIX_CTRL_HS400_MODE_MASK; in USDHC_EnableHS400Mode()
1215 base->MIX_CTRL &= ~USDHC_MIX_CTRL_HS400_MODE_MASK; in USDHC_EnableHS400Mode()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h21693 __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ member
DRV32M1_zero_riscy.h22521 __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ member