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Searched refs:MDACFG (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_xrdc.h726 assert(base->MDACFG[master] & XRDC_MDACFG_NCM_MASK); in XRDC_SetNonProcessorDomainAssignment()
728 …assert(assignIndex < ((base->MDACFG[master] & XRDC_MDACFG_NMDAR_MASK) >> XRDC_MDACFG_NMDAR_SHIFT)); in XRDC_SetNonProcessorDomainAssignment()
775 assert(!(base->MDACFG[master] & XRDC_MDACFG_NCM_MASK)); in XRDC_SetProcessorDomainAssignment()
777 …assert(assignIndex < ((base->MDACFG[master] & XRDC_MDACFG_NMDAR_MASK) >> XRDC_MDACFG_NMDAR_SHIFT)); in XRDC_SetProcessorDomainAssignment()
798 …assert(assignIndex < ((base->MDACFG[master] & XRDC_MDACFG_NMDAR_MASK) >> XRDC_MDACFG_NMDAR_SHIFT)); in XRDC_LockMasterDomainAssignment()
821 …assert(assignIndex < ((base->MDACFG[master] & XRDC_MDACFG_NMDAR_MASK) >> XRDC_MDACFG_NMDAR_SHIFT)); in XRDC_SetMasterDomainAssignmentValid()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h23261 …__I uint8_t MDACFG[37]; /**< Master Domain Assignment Configuration Regis… member
DRV32M1_zero_riscy.h30793 …__I uint8_t MDACFG[37]; /**< Master Domain Assignment Configuration Regis… member