Home
last modified time | relevance | path

Searched refs:MCFGR1 (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_lpi2c.c361 value = base->MCFGR1; in LPI2C_MasterInit()
365 base->MCFGR1 = value; in LPI2C_MasterInit()
372 prescaler = (base->MCFGR1 & LPI2C_MCFGR1_PRESCALE_MASK) >> LPI2C_MCFGR1_PRESCALE_SHIFT; in LPI2C_MasterInit()
431 …base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_MATCFG_MASK) | LPI2C_MCFGR1_MATCFG(config->matchMode); in LPI2C_MasterConfigureDataMatch()
513 base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_PRESCALE_MASK) | LPI2C_MCFGR1_PRESCALE(bestPre); in LPI2C_MasterSetBaudRate()
535 base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; in LPI2C_MasterStart()
963 base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; in LPI2C_MasterTransferNonBlocking()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h10223 …__IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x2… member
DRV32M1_zero_riscy.h10367 …__IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x2… member