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Searched refs:MCFGR0 (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_lpi2c.c353 value = base->MCFGR0; in LPI2C_MasterInit()
358 base->MCFGR0 = value; in LPI2C_MasterInit()
432 …base->MCFGR0 = (base->MCFGR0 & ~LPI2C_MCFGR0_RDMO_MASK) | LPI2C_MCFGR0_RDMO(config->rxDataMatchOnl… in LPI2C_MasterConfigureDataMatch()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h10222 …__IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x2… member
DRV32M1_zero_riscy.h10366 …__IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x2… member