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Searched refs:LPSPI_CR_MEN_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_lpspi.h492 base->CR |= LPSPI_CR_MEN_MASK; in LPSPI_Enable()
496 base->CR &= ~LPSPI_CR_MEN_MASK; in LPSPI_Enable()
Dfsl_lpspi.c345 if ((!LPSPI_IsMaster(base)) || (base->CR & LPSPI_CR_MEN_MASK)) in LPSPI_MasterSetBaudRate()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h11594 #define LPSPI_CR_MEN_MASK (0x1U) macro
11600 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
DRV32M1_zero_riscy.h11738 #define LPSPI_CR_MEN_MASK (0x1U) macro
11744 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)