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Searched refs:LPSPI_CFGR1_PCSCFG_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h11888 #define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) macro
11894 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
DRV32M1_zero_riscy.h12032 #define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) macro
12038 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)