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Searched refs:LPSPI_CFGR1_MASTER_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_lpspi.h709 base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode); in LPSPI_SetMasterSlaveMode()
720 return (bool)((base->CFGR1) & LPSPI_CFGR1_MASTER_MASK); in LPSPI_IsMaster()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h11824 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
11830 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
DRV32M1_zero_riscy.h11968 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
11974 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)