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Searched refs:LPIT_MCR_SW_RST_MASK (Results 1 – 5 of 5) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_lpit.h363 base->MCR |= LPIT_MCR_SW_RST_MASK; in LPIT_Reset()
364 base->MCR &= ~LPIT_MCR_SW_RST_MASK; in LPIT_Reset()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
Dsystem_RV32M1_zero_riscy.c473 SYSTICK_LPIT->MCR |= LPIT_MCR_SW_RST_MASK;
474 SYSTICK_LPIT->MCR &= ~LPIT_MCR_SW_RST_MASK;
Dsystem_RV32M1_ri5cy.c470 SYSTICK_LPIT->MCR |= LPIT_MCR_SW_RST_MASK;
471 SYSTICK_LPIT->MCR &= ~LPIT_MCR_SW_RST_MASK;
DRV32M1_ri5cy.h11254 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
11260 … (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK)
DRV32M1_zero_riscy.h11398 #define LPIT_MCR_SW_RST_MASK (0x2U) macro
11404 … (((uint32_t)(((uint32_t)(x)) << LPIT_MCR_SW_RST_SHIFT)) & LPIT_MCR_SW_RST_MASK)