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Searched refs:LPFLLCSR (Results 1 – 4 of 4) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_clock.c702 SCG->LPFLLCSR = config->trimConfig->trimMode; in CLOCK_InitLpFll()
704 if (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLERR_MASK) in CLOCK_InitLpFll()
711 SCG->LPFLLCSR |= (SCG_LPFLLCSR_LPFLLEN_MASK | config->enableMode); in CLOCK_InitLpFll()
714 while (!(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK)) in CLOCK_InitLpFll()
721 while (!(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK)) in CLOCK_InitLpFll()
731 uint32_t reg = SCG->LPFLLCSR; in CLOCK_DeinitLpFll()
745 SCG->LPFLLCSR = SCG_LPFLLCSR_LPFLLERR_MASK; in CLOCK_DeinitLpFll()
756 if (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK) /* LPFLL is valid. */ in CLOCK_GetLpFllFreq()
Dfsl_clock.h1545 return (bool)(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK); in CLOCK_IsLpFllValid()
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h16203 …__IO uint32_t LPFLLCSR; /**< Low Power FLL Control Status Register, offse… member
DRV32M1_zero_riscy.h17031 …__IO uint32_t LPFLLCSR; /**< Low Power FLL Control Status Register, offse… member