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Searched refs:LLWU_ME_Reserved3_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h8646 #define LLWU_ME_Reserved3_MASK (0x8U) macro
8652 … (((uint32_t)(((uint32_t)(x)) << LLWU_ME_Reserved3_SHIFT)) & LLWU_ME_Reserved3_MASK)
DRV32M1_zero_riscy.h8790 #define LLWU_ME_Reserved3_MASK (0x8U) macro
8796 … (((uint32_t)(((uint32_t)(x)) << LLWU_ME_Reserved3_SHIFT)) & LLWU_ME_Reserved3_MASK)