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Searched refs:LLWU0_BASE (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h9600 #define LLWU0_BASE (0x40024000u) macro
9602 #define LLWU0 ((LLWU_Type *)LLWU0_BASE)
9608 #define LLWU_BASE_ADDRS { LLWU0_BASE, LLWU1_BASE }
DRV32M1_zero_riscy.h9744 #define LLWU0_BASE (0x40024000u) macro
9746 #define LLWU0 ((LLWU_Type *)LLWU0_BASE)
9752 #define LLWU_BASE_ADDRS { LLWU0_BASE, LLWU1_BASE }