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Searched refs:INTMUX_CHn_CSR_IRQP_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h8188 #define INTMUX_CHn_CSR_IRQP_MASK (0x80000000U) macro
8194 … (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQP_SHIFT)) & INTMUX_CHn_CSR_IRQP_MASK)
DRV32M1_zero_riscy.h8332 #define INTMUX_CHn_CSR_IRQP_MASK (0x80000000U) macro
8338 … (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQP_SHIFT)) & INTMUX_CHn_CSR_IRQP_MASK)