Home
last modified time | relevance | path

Searched refs:GENFSK_XCVR_CTRL_CMDDEC_CS_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h24312 #define GENFSK_XCVR_CTRL_CMDDEC_CS_MASK (0x7000000U) macro
24314 …(uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_CMDDEC_CS_SHIFT)) & GENFSK_XCVR_CTRL_CMDDEC_CS_MASK)
DRV32M1_zero_riscy.h6909 #define GENFSK_XCVR_CTRL_CMDDEC_CS_MASK (0x7000000U) macro
6911 …(uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_CMDDEC_CS_SHIFT)) & GENFSK_XCVR_CTRL_CMDDEC_CS_MASK)