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Searched refs:GENFSK_XCVR_CFG_RX_WARMUP_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h24411 #define GENFSK_XCVR_CFG_RX_WARMUP_MASK (0xFF0000U) macro
24413 …(((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_RX_WARMUP_SHIFT)) & GENFSK_XCVR_CFG_RX_WARMUP_MASK)
DRV32M1_zero_riscy.h7008 #define GENFSK_XCVR_CFG_RX_WARMUP_MASK (0xFF0000U) macro
7010 …(((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_RX_WARMUP_SHIFT)) & GENFSK_XCVR_CFG_RX_WARMUP_MASK)