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Searched refs:GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h24392 #define GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_MASK (0x2U) macro
24394 …(((uint32_t)(x)) << GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT)) & GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_MASK)
DRV32M1_zero_riscy.h6989 #define GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_MASK (0x2U) macro
6991 …(((uint32_t)(x)) << GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT)) & GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_MASK)