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Searched refs:GENFSK_WHITEN_CFG_WHITEN_END_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h24677 #define GENFSK_WHITEN_CFG_WHITEN_END_MASK (0x4U) macro
24683 …t32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_END_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_END_MASK)
DRV32M1_zero_riscy.h7274 #define GENFSK_WHITEN_CFG_WHITEN_END_MASK (0x4U) macro
7280 …t32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_END_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_END_MASK)