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Searched refs:GENFSK_WHITEN_CFG_MANCHESTER_INV_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h24714 #define GENFSK_WHITEN_CFG_MANCHESTER_INV_MASK (0x2000U) macro
24720 …(uint32_t)(x)) << GENFSK_WHITEN_CFG_MANCHESTER_INV_SHIFT)) & GENFSK_WHITEN_CFG_MANCHESTER_INV_MASK)
DRV32M1_zero_riscy.h7311 #define GENFSK_WHITEN_CFG_MANCHESTER_INV_MASK (0x2000U) macro
7317 …(uint32_t)(x)) << GENFSK_WHITEN_CFG_MANCHESTER_INV_SHIFT)) & GENFSK_WHITEN_CFG_MANCHESTER_INV_MASK)