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Searched refs:GENFSK_T1_CMP_T1_CMP_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h24261 #define GENFSK_T1_CMP_T1_CMP_MASK (0xFFFFFFU) macro
24263 … (((uint32_t)(((uint32_t)(x)) << GENFSK_T1_CMP_T1_CMP_SHIFT)) & GENFSK_T1_CMP_T1_CMP_MASK)
DRV32M1_zero_riscy.h6858 #define GENFSK_T1_CMP_T1_CMP_MASK (0xFFFFFFU) macro
6860 … (((uint32_t)(((uint32_t)(x)) << GENFSK_T1_CMP_T1_CMP_SHIFT)) & GENFSK_T1_CMP_T1_CMP_MASK)