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Searched refs:GENFSK_PACKET_CFG_SYNC_ADDR_SZ_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h24564 #define GENFSK_PACKET_CFG_SYNC_ADDR_SZ_MASK (0xC0U) macro
24566 …t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_SYNC_ADDR_SZ_SHIFT)) & GENFSK_PACKET_CFG_SYNC_ADDR_SZ_MASK)
DRV32M1_zero_riscy.h7161 #define GENFSK_PACKET_CFG_SYNC_ADDR_SZ_MASK (0xC0U) macro
7163 …t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_SYNC_ADDR_SZ_SHIFT)) & GENFSK_PACKET_CFG_SYNC_ADDR_SZ_MASK)