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Searched refs:GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3 (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h24497 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTR… macro
DRV32M1_zero_riscy.h7094 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTR… macro