Home
last modified time | relevance | path

Searched refs:GENFSK_IRQ_CTRL_T2_IRQ_EN_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h24188 #define GENFSK_IRQ_CTRL_T2_IRQ_EN_MASK (0x200000U) macro
24194 …(((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T2_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_T2_IRQ_EN_MASK)
DRV32M1_zero_riscy.h6785 #define GENFSK_IRQ_CTRL_T2_IRQ_EN_MASK (0x200000U) macro
6791 …(((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T2_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_T2_IRQ_EN_MASK)