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Searched refs:GENFSK_H1_CFG_H1_MASK_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h24609 #define GENFSK_H1_CFG_H1_MASK_MASK (0xFFFF0000U) macro
24611 … (((uint32_t)(((uint32_t)(x)) << GENFSK_H1_CFG_H1_MASK_SHIFT)) & GENFSK_H1_CFG_H1_MASK_MASK)
DRV32M1_zero_riscy.h7206 #define GENFSK_H1_CFG_H1_MASK_MASK (0xFFFF0000U) macro
7208 … (((uint32_t)(((uint32_t)(x)) << GENFSK_H1_CFG_H1_MASK_SHIFT)) & GENFSK_H1_CFG_H1_MASK_MASK)