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Searched refs:GATE3 (Results 1 – 3 of 3) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/drivers/
Dfsl_sema42.h81 #define SEMA42_GATEn(base, n) (*(&((base)->GATE3) + ((n) ^ 3U)))
/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h17296 __IO uint8_t GATE3; /**< Gate Register, offset: 0x0 */ member
DRV32M1_zero_riscy.h18124 __IO uint8_t GATE3; /**< Gate Register, offset: 0x0 */ member