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Searched refs:FTFE_SACCSH_SA_S_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h7196 #define FTFE_SACCSH_SA_S_MASK (0xFFU) macro
7198 … (((uint8_t)(((uint8_t)(x)) << FTFE_SACCSH_SA_S_SHIFT)) & FTFE_SACCSH_SA_S_MASK)
DRV32M1_zero_riscy.h6558 #define FTFE_SACCSH_SA_S_MASK (0xFFU) macro
6560 … (((uint8_t)(((uint8_t)(x)) << FTFE_SACCSH_SA_S_SHIFT)) & FTFE_SACCSH_SA_S_MASK)