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Searched refs:FTFE_SACCH0_SA_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h7140 #define FTFE_SACCH0_SA_MASK (0xFFU) macro
7142 … (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH0_SA_SHIFT)) & FTFE_SACCH0_SA_MASK)
DRV32M1_zero_riscy.h6502 #define FTFE_SACCH0_SA_MASK (0xFFU) macro
6504 … (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH0_SA_SHIFT)) & FTFE_SACCH0_SA_MASK)